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1 typical a pplica t ion descrip t ion micropower usb power manager with li-ion charger and two step-down regulators the ltc ? 3554 family* are micropower, highly integrated power management and battery charger ics for single-cell li-ion/polymer battery applications. they include a powerpath? manager with automatic load prioritization, a batter y charger , an ideal diode and numerous internal protection features. designed specifically for usb applica - tions, the ltc3554 power managers automatically limit input current to a maximum of either 100ma or 500ma. battery charge current is automatically reduced such that the sum of the load current and the charge current does not exceed the selected input current limit. the l tc3554 also includes two synchronous step-down switching regulators as well as a pushbutton controller. with all supplies enabled in standby mode, the quiescent current drawn from the battery is only 10a. the ltc3554 family are available in a 3mm 3mm 0.75mm 20-lead qfn package. battery drain current vs temperature fea t ures a pplica t ions n 10a standby mode quiescent current (all outputs on) n seamless transition between input power sources: li-ion/polymer battery and usb n 240m internal ideal diode n dual high efficiency step-down switching regulators (200ma i out ) with adjustable output voltages n pushbutton on/off control with system reset n reset time: 5 sec (ltc3554/ltc3554-1), 14 sec (ltc3554-2/l tc3554-3) n full featured li-ion/polymer battery charger n programmable charge current with thermal limiting n instant-on operation with discharged battery n battery float voltage: 4.2v (ltc3554/ltc3554-2/ l tc3554-3), 4.1v (ltc3554-1) n 3mm 3mm 0.75mm 20-lead qfn package n usb-based handheld products n portable li-ion/polymer based electronic devices n fitness computers n low power medical devices v bus ntc prog hpwr susp pwr_on1 fsel stby pgood pwr_on2 pbstat on v out chrg bat bvin sw1 fb1 sw2 fb2 on/off li-ion battery 100k 100k t 1.87k 10pf 10f 2.2f 2.05m 649k 3.3v 200ma 4.7h 10pf 10f 332k 649k 1.2v 200ma 3554 ta01a 10h system load 4.35v to 5.5v usb input ltc3554 + 10f 10f temperature (c) ?75 ?50 ?25 25 50 75 100 125 0 0 battery drain current (a) 4 6 10 14 12 8 3554 ta01b 2 both regulators disabled one regulator enabled hard reset both regulators enabled v bat = 3.8v stby = 3.8v regulators load = 0ma l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and powerpath, hot swap and bat-track are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6522118, 6700364, 5481178, 6304066, 6570372, 6580258, 7511390. *see table on page 2 for available options. ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v bus , v out , bvin t < 1m s and duty cycle < 1% ................... C 0.3v to 7v st eady state ............................................ C 0.3v to 6v bat, ntc, chrg , susp, pbstat, on , pgood, fb1, fb2 .................................. C 0.3v to 6v pwr_on1, pwr_on2, stby hpwr, fsel (note 4) ...................... C 0.3v to v cc + 0.3v i bat ............................................................................. 1a i sw1 , i sw2 (continuous) ...................................... 3 00ma i chrg , i pgood, i pbstat ............................................ 75m a operating junction temperature range ... C 40c to 85c junction temperature ............................................ 11 0c storage temperature range .................. C 65c to 125c (notes 1, 2, 3) o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc3554eud#pbf ltc3554eud#trpbf ldys 20-lead (3mm 3mm) plastic qfn C40c to 85c ltc3554eud-1#pbf ltc3554eud-1#trpbf lgfg 20-lead (3mm 3mm) plastic qfn C40c to 85c ltc3554eud-2#pbf ltc3554eud-2#trpbf lfzx 20-lead (3mm 3mm) plastic qfn C40c to 85c ltc3554eud-3#pbf ltc3554eud-3#trpbf lghk 20-lead (3mm 3mm) plastic qfn C40c to 85c ltc3554epd#pbf ltc3554epd#trpbf fdpt 20-lead (3mm 3mm) plastic utqfn C40c to 85c (obsolete) consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www .linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 20 19 18 17 16 7 8 top view 21 gnd ud package 20-lead (3mm 3mm) plastic qfn 9 10 hpwr fsel pbstat pgood on ntc chrg sw1 bvin sw2 v bus susp v out bat prog fb1 fb2 pwr_on2 pwr_on1 stby 12 11 13 14 15 4 5 3 2 1 6 t jmax = 110c, ja = 58.7c/w exposed pad (pin 21) is gnd, and must be soldered to pcb gnd ltc3554 options part number float voltage hard reset time sequencing ltc3554 4.2v 5 seconds yes (buck1 buck2) ltc3554-1 4.1v 5 seconds yes (buck1 buck2) ltc3554-2 4.2v 14 seconds yes (buck1 buck2) ltc3554-3 4.2v 14 seconds no (buck1 and buck2 together) ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
3 p ower manager e lec t rical c harac t eris t ics the l denotes specifications that apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2), v bus = 5v, v b at = 3.8v, hpwr = susp = pwr_on1 = pwr_on2 = 0v, r prog = 1.87k, stby = high, unless otherwise noted. symbol parameter conditions min typ max units no-load quiescent currents i batq battery drain current i out = 0 (note 5) v bus = 0v (hard reset) v bus = 0v v bus = 0v, pwr_on1 = pwr_on2 = 3.8v 0.2 3 6.5 2 5 12 a a a i batqc battery drain current, v bus available v bat = v float , timer timed out 5 8 a i busq v bus input current 100ma, 500ma modes susp = 5v (suspend mode) 300 15 500 30 a a i bvinq bvin input current shutdown input current one buck enabled, standby mode both bucks enabled, standby mode one buck enabled both bucks enabled v bvin = 3.8v, v bus = 0v (note 8) pwr_on1 = stby = 3.8v pwr_on1 = pwr_on2 = stby = 3.8v pwr_on1 = 3.8v, stby = 0v pwr_on1 = pwr_on2 = 3.8v, stby = 0v 0.01 1.5 3 18 36 1 3 6 35 70 a a a a a input power supply v bus input supply voltage 4.35 5.5 v i bus(lim) total input current hpwr = 0v (100ma) hpwr = 5v (500ma) l l 80 400 90 450 100 500 ma ma v uvlo v bus undervoltage lockout rising threshold falling threshold 3.5 3.8 3.6 3.9 v v v duvlo v bus to bat differential undervoltage lockout rising threshold falling threshold 0 200 50 300 mv mv r on_ilim input current limit power fet on-resistance (between v bus and v out ) 350 m battery charger v float v bat regulated output voltage ltc3554/ltc3554-2/ltc3554-3 ltc3554/ltc3554-2/ltc3554-3, 0c < t a < 85c ltc3554-1 ltc3554-1, 0c < t a < 85c 4.179 4.165 4.079 4.065 4.2 4.2 4.1 4.1 4.221 4.235 4.121 4.135 v v v v i chg constant-current mode charge current r prog = 1.87k, 0 t a 85c 380 400 420 ma v prog v prog,trkl prog pin servo voltage prog pin servo voltage in trickle charge v bat < v trkl 1 0.1 v v h prog ratio of i bat to prog pin current 750 ma/ma i trkl trickle charge current v bat < v trkl 30 40 50 ma v trkl trickle charge threshold voltage v bat rising v bat falling 2.6 2.9 2.75 3 v v v rechrg recharge battery threshold voltage threshold voltage relative to v float C75 C100 C115 mv t term safety timer termination period timer starts when v bat = v float C 50mv 3.2 4 5 hour t badbat bad battery termination time v bat < v trkl 0.4 0.5 0.63 hour h c/10 end-of-charge indication current ratio (note 6) 0.085 0.1 0.115 ma/ma r on_chg battery charger power fet on-resistance (between v out and bat) i bat = 200ma 220 m t lim junction temperature in constant temperature mode 110 c ntc v cold cold temperature fault threshold voltage rising ntc voltage hysteresis 75 76 1.3 77 %v bus %v bus v hot hot temperature fault threshold voltage falling ntc voltage hysteresis 34 35 1.3 36 %v bus %v bus ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
4 power m anager e lec t rical c harac t eris t ics the l denotes specifications that apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2), v bus = 5v, v b at = 3.8v, hpwr = susp = pwr_on1 = pwr_on2 = 0v, r prog = 1.87k, stby = high, unless otherwise noted. symbol parameter conditions min typ max units v dis ntc disable threshold voltage falling ntc voltage hysteresis l 1.2 1.7 50 2.2 %v bus mv i ntc ntc leakage current v ntc = v bus = 5v C50 50 na ideal diode v fwd forward voltage detection (note 12) 15 mv r dropout diode on-resistance, dropout i out = 200ma, v bus = 0v 240 m i max diode current limit (note 7) 1 a logic inputs (hpwr, susp) v il input low voltage 0.4 v v ih input high voltage 1.2 v r pd internal pull-down resistance 4 m logic output (chrg) v ol output low voltage i chrg = 5ma 65 250 mv i chrg output hi-z leakage current v bat = 4.5v, v chrg = 5v 0 1 a symbol parameter conditions min typ max units bvin input supply voltage (note 9) l 2.7 5.5 v v out uvlo v out falling v out rising bvin connected to v out through low impedance. v out uvlo disables the switching regulators. 2.5 2.6 2.8 2.9 v v f osc oscillator frequency fsel high fsel low 1.91 0.955 2.25 1.125 2.59 1.295 mhz mhz i fb1 i fb2 fb1 input current (note 8) fb2 input current (note 8) C0.05 C0.05 0.05 0.05 a a r sw1_pd r sw2_pd sw1 pull-down in shutdown sw2 pull-down in shutdown p wr_on1 = 0v p wr_on2 = 0v 10 10 k k logic input pins (fsel, stby) input high voltage 1.2 v input low v oltage 0.4 v input current C1 1 a switching regulator 1 in normal operation (stby low) i lim1 peak pmos current limit pwr_on1 = 3.8v (note 7) 300 450 600 ma v fb1 regulated feedback voltage pwr_on1 = 3.8v l 780 800 820 mv d1 max duty cycle 100 % r p1 r ds(on) of pmos i sw1 = 100ma 1.1 r n1 r ds(on) of nmos i sw1 = C100ma 0.7 switching regulator 1 in standby mode (stby high) v fb1_low feedback voltage threshold pwr_on1 = 3.8v, v fb1 falling l 770 800 820 mv i short1_sb short-circuit current 10 21 50 ma v drop1_sb standby mode dropout voltage pwr_on1 = 2.9v, i sw1 = 5ma, v fb1 = 0.77v, v out = 2.9v, bvin = 2.9v 25 60 mv s wi t ching r egula t or e lec t rical c harac t eris t ics the l denotes specifications that apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v out = bvin = 3.8v, pwr_on1 = pwr_on2 = 0v, unless otherwise noted. ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
5 s wi t ching r egula t or e lec t rical c harac t eris t ics pushbu tt on in t er f ace e lec t rical c harac t eris t ics the l denotes specifications that apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v out = bvin = 3.8v, pwr_on1 = pwr_on2 = 0v, unless otherwise noted. the l denotes specifications that apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v b at = 3.8v, unless otherwise noted. symbol parameter conditions min typ max units switching regulator 2 in normal operation (stby low) i lim2 peak pmos current limit pwr_on2 = 3.8v (note 7) 300 450 600 ma v fb2 regulated feedback voltage pwr_on2 = 3.8v l 780 800 820 mv d2 max duty cycle 100 % r p2 r ds(on) of pmos i sw2 = 100ma 1.1 r n2 r ds(on) of nmos i sw2 = C100ma 0.7 switching regulator 2 in standby mode (stby high) v fb2_low feedback voltage threshold pwr_on2 = 3.8v, v fb2 falling l 770 800 820 mv i short2_sb short-circuit current 10 21 50 ma v drop2_sb standby mode dropout voltage pwr_on2 = 2.9v, i sw2 = 5ma, v fb2 = 0.77v, v out = 2.9v, bvin = 2.9v 25 60 mv symbol parameter conditions min typ max units pushbutton pin (on) v cc_pb pushbutton operating supply range (notes 4 , 9) l 2.7 5.5 v v on_th on threshold rising on threshold falling 0.4 1.2 v v i on on input current v on = v cc (note 4) C1 1 a r pb_pu pushbutton pull-up resistance pull-up to v cc (note 4) 200 400 650 k logic input pins (pwr_on1, pwr_on2) v pwr_onx pwr_onx threshold rising pwr_onx threshold falling 0.4 1.2 v v i pwr_onx pwr_onx input current C1 1 a status output pins (pbstat, pgood) i pbstat pbstat output high leakage current v pbstat = 3v C1 1 a v pbstat pbstat output low voltage i pbstat = 3ma 0.1 0.4 v i pgood pgood output high leakage current v pgood = 3v C1 1 a v pgood pgood output low voltage i pgood = 3ma 0.1 0.4 v v thpgood pgood threshold voltage (note 10) C8 % pushbutton timing parameters (note 11) t on _pbstatl minimum on low time to cause pbstat low on brought low during power-on (pon) or power-up (pup1, pup2) states 50 ms t on_ pbstath delay from on high to pbstat high power-on (pon) state, after pbstat has been low for at least t pbstat_pw 900 s t on_pup minimum on low time to enter power-up (pup1 or pup2) state starting in the hard reset (hr) or power -off (poff) states 400 ms t on_hr minimum on low time to hard reset on brought low during the power-on (pon)or power-up (pup1, pup2) states ltc3554/ltc3554-1 ltc3554-2/ltc3554-3 4 11 5 14 6 17 s s t pbstat_pw pbstat minimum pulse width power-on (pon) or power-up (pup1, pup2) states 40 50 ms ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
6 note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3554 is tested under pulsed load conditions such that t j t a . the ltc3554 are guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 85c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 3. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 110c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. note 4. v cc is the greater of v bus or bat. note 5. total battery drain current is the sum of i batq and i out. for example, in applications where the buck input (bvin pin) is connected to the powerpath output (v out pin) such that i out = i bvin , total battery drain current = i batq + i bvin . note 6. hc/10 is expressed as a fraction of programmed full charge current with specified prog resistor. note 7. the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the absolute maximum specified pin current rating may result in device degradation or failure. note 8. fb high, not switching note 9. v out not in uvlo. note 10. pgood threshold is expressed as a percentage difference from the buck regulation voltage. the threshold is measured with the buck feedback pin voltage rising. note 11. see the operation section of this data sheet for detailed explanation of the pushbutton state machine and the effects of each state on switching regulator and power manager operation. note 12. if v bus < v uvlo then v fwd = 0 and the forward voltage across the ideal diode is equal to its current times r dropout . pushbu tt on in t er f ace e lec t rical c harac t eris t ics the l denotes specifications that apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v b at = 3.8v, unless otherwise noted. symbol parameter conditions min typ max units t extpwr power-up from usb present to power-up (pup1 or pup2) state starting in the hard reset (hr) or power-off (poff) states 100 ms t pon_up any pwr_onx high to power-on state starting with both pwr_onx low in the power- off (poff) state 900 s t pon_dis pwr_onx low to buckx disabled 1 s t pup power-up (pup1 or pup2) state duration 5 s t pdn power-down (pdn1 or pdn2) state duration 1 s t pgoodh bucks in regulation to pgood high all enabled bucks within pgood threshold voltage 230 ms t pgoodl bucks disabled to pgood low all bucks disabled 100 s ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
7 v bus supply current vs temperature v bus supply current vs temperature (suspend mode) battery drain current vs temperature v bus current limit vs temperature typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise specified. temperature (c) ?75 200 i bus (a) 300 350 400 ?25 25 50 150 3554 g01 250 ?50 0 75 100 125 v bus = 5v hpwr = l temperature (c) ?75 0 i bus (a) 10 15 25 20 ?25 25 50 150 3554 g02 5 ?50 0 75 100 125 v bus = 5v temperature (c) ?75 ?50 ?25 25 50 75 100 125 0 0 battery drain current (a) 4 6 10 14 12 8 3554 g03 2 both regulators disabled one regulator enabled hard reset both regulators enabled v bat = 3.8v stby = 3.8v regulators load = 0ma temperature (c) ?75 0 i bat (a) 2 3 5 4 ?25 25 50 150 3554 g03b 1 ?50 0 75 100 125 v bus = 5v v bat = 3.8v temperature (c) ?75 0 i vbus (ma) 200 300 500 400 ?25 25 50 3554 g04 100 ?50 0 75 100 125 v bus = 5v hpwr = h hpwr = l battery drain current vs temperature (suspend mode) load current (ma) 0 100 300 500 400 200 ?100 current (ma) 100 200 400 600 500 300 3554 g05 0 r prog = 1.87k i vbus i load i bat (charging) i bat (discharging) v bus and battery current vs load current battery charge current and voltage vs time (ltc3554/ltc3554-2/ltc3554-3) r on from v bus to v out vs temperature charge current vs temperature (thermal regulation) temperature (c) ?75 ?50 ?25 25 50 75 100 150125 0 0.20 r on () 0.30 0.35 0.45 0.50 0.40 3554 g05a 0.25 i out = 200ma temperature (c) ?75 0 i bat (ma) 160 240 480 400 320 ?25 25 50 150 3554 g06 80 ?50 0 75 100 125 v bus = 5v hpwr = h r prog = 1.87k time (hour) 0 0 battery current (ma) voltage (v) 200 300 600 500 400 2 4 5 3554 g07 100 0 2 3 6 5 4 1 1 3 6 7 8 920mahr cell v bus = 5v r prog = 1.87k chrg v bat safety timer termination c/10 i bat ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
8 typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise specified. forward voltage vs ideal diode current v bus connect waveform v bus disconnect waveform i bat (ma) 0 400200 0 v fwd (mv) 100 150 250 300 200 1000 1200 3554 g11 50 800600 v bus = 5v v bus = 0v v bat = 3.75v i out = 100ma r prog = 2k 1ms/div 5v 5v v bus v out 0 0 0a 0a i bus 0.5a/div i bat 0.5a/div 3554 g12 v bat = 3.75v i out = 100ma r prog = 2k 3554 g13 50s/div 5v 5v v bus v out 0 0 0a 0a i bus 0.5a/div i bat 0.5a/div oscillator frequency vs temperature switching from suspend mode to 500ma mode v bat = 3.75v i out = 50ma r prog = 2k 3554 g15 1ms/div 5v 5v susp v out 0 0 0a 0a i bus 0.5a/div i bat 0.5a/div switching from 100ma mode to 500ma mode v bat = 3.75v i out = 50ma r prog = 2k 3554 g14 1ms/div 5v hpwr 0 0a 0a i bus 0.5a/div i bat 0.5a/div temperature (c) ?75 ?50 ?25 25 50 75 100 150125 0 1.9 oscillator frequency (mhz) 2.1 2.2 2.4 2.6 2.5 2.3 3554 g16 2.0 2.7v 3.8v 5.5v i b at vs v b at (ltc3554/ltc3554-2/ltc3554-3) v float load regulation battery regulation (float) voltage vs temperature v bat (v) 2 2.4 3.6 4 3.22.8 0 i bat (ma) 200 300 500 400 3554 g10 100 4.4 v bus = 5v hpwr = h r prog = 1.87k i bat (ma) 0 50 4.08 v float (v) 4.12 4.14 4.22 4.20 4.18 4.16 200150 250 350 450 400 3554 g08 4.10 100 300 v bus = 5v hpwr = h ltc3554/ltc3554-2/ltc3554-3 ltc3554-1 temperature (c) ?75 ?25?50 4.08 v float (v) 4.16 4.18 4.22 4.20 50 100 125 3554 g09 4.14 4.12 4.10 250 75 v bus = 5v i bat = 2ma ltc3554/ltc3554-2/ltc3554-3 ltc3554-1 ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
9 typical p er f or m ance c harac t eris t ics burst mode ? bv in supply current per enabled step-down switching regulator standby mode bv in supply current per enabled step-down switching regulator step-down switching regulator 1 3.3v output efficiency vs i out1 step-down switching regulator 2 1.8v output efficiency vs i out2 t a = 25c, unless otherwise specified. step-down switching regulator 1 2.5v output efficiency vs i out1 step-down switching regulator 2 1.2v output efficiency vs i out2 i out1 (ma) 0.01 0.1 0 efficiency (%) 70 100 1 10 100 1000 3554 g24a 60 50 40 30 20 10 80 90 fsel = l stby = l 3.8v 5v i out2 (ma) 0.01 0.1 0 efficiency (%) 70 100 1 10 100 1000 3554 g25 60 50 40 30 20 10 80 90 fsel = l stby = l 3.8v 5v bv in supply voltage (v) 2.5 3 4 4.5 5.55 3.5 0 bv in supply current (a) 10 15 25 35 30 20 3554 g17 5 no load stby = l ?45c 25c 90c bv in supply voltage (v) 2.5 3 4 4.5 5.55 3.5 0 bv in supply current (a) 1.0 1.5 2.5 3.0 2.0 3554 g18 0.5 no load stby = h ?45c 25c 90c i out1 (ma) efficiency (%) 3554 g31 0.01 0.1 100 1000 101 0 20 30 80 40 50 60 90 100 70 10 fsel = l stby = l 3.8v 5v i out2 (ma) efficiency (%) 3554 g32 0.01 0.1 100 1000 101 0 20 30 80 40 50 60 90 100 70 10 fsel = l stby = l 3.8v 5v step-down switching regulator output transient step-down switching regulator short-circuit current vs temperature temperature (c) ?75 ?50 ?25 25 50 75 100 150125 0 400 short circuit current (ma) 440 460 500 480 3554 g19 420 stby = l v out2 = 1.2v stby = h v out2 20mv/div (ac) 5ma 10a i out2 3554 g26 50s/div step-down switching regulator output transient v out1 = 3.3v stby = l v out1 100mv/div (ac) 150ma 5ma i out1 3554 g27 200s/div ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
10 typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise specified. step-down switching regulator start-up waveform v out2 = 1.2v i out2 = 50ma r out1 = 22 stby = l v out2 50mv/div (ac) v out1 1v/div i l1 100ma/div 0v pwr_on1 0ma 3554 g28 100s/div step-down switching regulator output transient (stby high to low) step-down switching regulator output transient (fsel low to high) v out1 = 3.3v i out1 = 100ma v out2 = 1.2v i out2 = 50ma stby = l v out2 20mv/div (ac) v out1 50mv/div (ac) fsel 3554 g29 50s/div v out1 = 3.3v i out1 = 5ma v out2 = 1.2v i out2 = 5ma v out2 20mv/div (ac) v out1 20mv/div (ac) stby 3554 g30 50s/div step-down switching regulator dropout voltage in standby mode vs load current load current (ma) 0 2 6 1412108 4 0 dropout voltage (mv) 20 40 100 200 160 180 140 120 80 60 3554 g23 v bvin = 2.9v v fbx = 780mv stby = h ?45c 25c 90c step-down switching regulator switch impedance vs temperature temperature (c) ?75 ?50 ?25 25 50 75 100 150125 0 0 switch impedance () 0.4 0.6 1.6 0.8 1.0 1.2 1.4 3554 g20 0.2 pmos nmos bv in = 3.2v stby = l step-down switching regulator feedback voltage vs output current output current (ma) feedback voltage (v) 3554 g21 0.1 1 100 1000 10 0.780 0.790 0.795 0.820 0.800 0.805 0.810 0.815 0.785 3.8v 5v stby = l ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
11 hpwr (pin 1): high power logic input. when this pin is low the input current limit is set to 100ma and when this pin is driven high it is set to 500ma. the susp pin needs to be low for the input current limit circuit to be enabled. this pin has a conditional internal pull-down resistor when power is applied to the v bus pin. fsel (pin 2): buck frequency select. when this pin is low the buck switching frequency is set to 1.125mhz and when this pin is driven high it is set to 2.25mhz. pbstat (pin 3): pushbutton status. this open-drain output is a debounced and buffered version of the on pushbut - ton input. it may be used to interrupt a microprocessor. pgood (pin 4): power good. this open-drain output indicates that all enabled buck regulators have been in regulation for at least 230ms. on (pin 5): pushbutton input. weak internal pull-up forces a high state if on is left floating. a normally open pushbutton is connected from on to ground to force a low state on this pin. fb1 (pin 6): feedback input for step-down switching regulator 1. this pin servos to a fixed voltage of 0.8v when the control loop is complete. fb2 (pin 7): feedback input for step-down switching regulator 2. this pin servos to a fixed voltage of 0.8v when the control loop is complete. pwr_on2 (pin 8): logic input enables step-down switch - ing regulator 2. pw r_on1 (pin 9): logic input enables step-down switch - ing regulator 1. stby (pin 10): standby mode. when this pin is driven high the part enters a ver y low quiescent current mode. the buck regulators are each limited to 5ma maximum load current in this mode. sw2 (pin 11): power transmission (switch) pin for step- down switching regulator 2. bvin (pin 12): power input for step-down switching regulators 1 and 2. it is recommended that this pin be connected to the v out pin. it should be bypassed with a low impedance multilayer ceramic capacitor. sw1 (pin 13): power transmission (switch) pin for step- down switching regulator 1. chrg (pin 14): open-drain charge status output. this pin indicates the status of the battery charger. it is internally pulled low while charging. once the battery charge cur - rent reduces to less than one-tenth of the programmed charge current, this pin goes into a high impedance state. an external pull-up resistor and/or led is required to provide indication. ntc (pin 15): the ntc pin connects to a batter ys therm - istor to determine if the battery is too hot or too cold to charge. if the batter y s temperature is out of range, charging is paused until it drops back into range. a low drift bias resistor is required from v bus to ntc and a thermistor is required from ntc to ground. if the ntc function is not desired, the ntc pin should be grounded. prog (pin 16): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current as given by: i chg (a) = 750v r prog if sufficient input power is available in constant-current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current. bat (pin 17): single-cell li-ion battery pin. depending on available power and load, a li-ion battery on bat will either deliver system power to v out through the ideal diode or be charged from the battery charger. v out (pin 18) : output voltage of the powerpath control - ler and input voltage of the battery charger. the majority of the portable products should be powered from v out . p in func t ions ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
12 p in func t ions the ltc3554 will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted input current from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance multilayer ceramic capacitor. susp (pin 19): suspend mode logic input. if this pin is driven high the input current limit path is disabled. in this state the circuit draws negligible power from the v bus pin. any load at the v out pin is provided by the battery through the internal ideal diode. when this input is grounded, the input current limit will be set to desired value as determined by the state of the hpwr pin. this pin has a conditional internal pull-down resistor when power is applied to the v bus pin. v bus (pin 20): usb input voltage. v bus will usually be connected to the usb port of a computer or a dc output wall adapter. v bus should be bypassed with a low imped - ance multilayer ceramic capacitor. gnd (exposed pad pin 21): ground. the exposed pack - age pad is ground and must be soldered to the pc board for proper functionality and for maximum heat transfer . ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
13 b lock diagra m 0.8v osc 200ma step-down dc/dc en stby input current limit cc/cv charger battery temp monitor power good comparators push button interface 2.25mhz/ 1.125mhz oscillator charge status 0.8v osc v bus v out bat prog sw1 fb1 bvin sw2 fb2 pgood hpwr susp ntc fsel extpwr uvlo stby gnd 3554 bd1 pwr_on1 pwr_on2 pbstat on chrg 200ma step-down dc/dc en stby 20 18 17 16 13 6 12 11 7 4 1 19 15 14 2 10 21 9 8 3 5 4096 ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
14 introduction the ltc3554 is a highly integrated power management ic that includes the following features: powerpath controller battery charger ideal diode pushbutton controller two step-down switching regulators designed specifically for usb applications, the powerpath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input current never violates the usb specifications. the ideal diode from bat to v out guarantees that ample power is always available to v out even if there is insufficient or absent power at v bus . the ltc3554 also includes a pushbutton input to control the two synchronous step- down switching regulators and system reset. the two constant-frequency current mode step-down switching regulators provide 200ma each and support 100% duty cycle operation as well as operating in burst mode operation for high efficiency at light load. no external compensation components are required for the switching regulators. either regulator can be programmed for a minimum out- put voltage of 0.8v and can be used to power a micro- controller core, microcontroller i/o, memor y or other logic circuitry. the buck regulators can be operated at 1.125mhz or 2.25mhz. they also include a low power standby mode which can be used to power essential keep-alive circuitry while draining ultralow current from the battery for extended battery life. usb powerpath controller the input current limit and charger control circuits of the ltc3554 are designed to limit input current as well as control battery charge current as a function of i vout . v out drives the combination of the external load, the two step-down switching regulators and the battery charger. if the combined load does not exceed the programmed input current limit, v out will be connected to v bus through an internal 350m p-channel mosfet. if the combined load at v out exceeds the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satisfied while maintaining the programmed input current. even if the battery charge current is set to exceed the allowable usb current, the average input current usb specification will not be violated. furthermore, load current at v out will always be prioritized and only excess available current will be used to charge the battery. the input current limit is programmed by the hpwr and susp pins. if susp pin set high, the input current limit is disabled. if susp pin is low, the input current limit is enabled. hpwr pin selects between 100ma input current limit when it is low and 500ma input current limit when it is high. op era t ion simplified powerpath block diagram 100ma/500ma input current limit cc/cv charger 15mv ideal 3554 f01 + ? v out 18 v bus 20 bat 17 ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
15 ideal diode from bat to v out the ltc3554 has an internal ideal diode from bat to v out designed to respond quickly whenever v out drops below bat. if the load increases beyond the input current limit, additional current will be pulled from the battery via the ideal diode. furthermore, if power to v bus (usb) is removed, then all of the application power will be provided by the battery via the ideal diode. the ideal diode is fast enough to keep v out from dropping significantly with just the recommended output capacitor. the ideal diode consists of a precision amplifier that enables an on-chip p-channel mosfet whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approximately 240m. suspend mode when the susp pin is pulled high the ltc3554 enters suspend mode to comply with the usb specification. in this mode, the power path between v bus and v out is put in a high impedance state to reduce the v bus input current to 15a. the system load connected to v out is supplied through the ideal diode connected to bat. v bus undervoltage lockout (uvlo) and undervoltage current limit (uvcl) an internal undervoltage lockout circuit monitors v bus and keeps the input current limit circuitry off until v bus rises above the rising uvlo threshold (3.8v) and at least 200mv above v bat . hysteresis on the uvlo turns off the input current limit circuitry if v bus drops below 3.6v or within 50mv of v bat . when this happens, system power at v out will be drawn from the battery via the ideal diode. to minimize the possibility of oscillation in and out of uvlo when using resistive input supplies, the input current limit is reduced as v bus falls below 4.45v typical. battery charger the ltc3554 includes a constant-current/constant-volt- age battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out of temperature charge pausing. when a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.9v, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. if the low voltage persists for more than 1/2 hour, the battery charger automatically terminates. once the battery voltage is above 2.9v, the battery charger begins charging in full power constant current mode. the current delivered to the battery will try to reach 750v/r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed current. the external load will always be prioritized over the battery charge current. the usb cur - rent limit programming will always be observed and only additional current will be available to charge the battery. when system loads are light, battery charge current will be maximized. charge termination the battery charger has a built-in safety timer. when the battery voltage approaches the float voltage (4.2v for ltc3554/ltc3554-2/ltc3554-3 or 4.1v for ltc3554-1), the charge current begins to decrease as the ltc3554 enters constant-voltage mode. once the battery charger detects that it has entered constant-voltage mode, the four hour safety timer is started. after the safety timer expires, charging of the battery will terminate and no more current will be delivered to the battery. op era t ion ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
16 automatic recharge after the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will automati - cally begin when the battery voltage falls below v rechrg (typically 4.1v for ltc3554/ltc3554-2/ltc3554-3 or 4v for ltc3554-1). in the event that the safety timer is running when the battery voltage falls below v rechrg , the timer will reset back to zero. to prevent brief excursions below v rechrg from resetting the safety timer, the battery volt - age must be below v rechrg for approximately 2ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus , is removed and then replaced). charge current the charge current is programmed using a single resistor from prog to ground. 1/750th of the battery charge cur - rent is delivered to prog which will attempt to servo to 1.000v . thus, the batter y charge current will try to reach 750 times the current in the prog pin. the program resistor and the charge current are calculated using the following equations: r prog = 750v i chg ,i chg = 750v r prog in either the constant-current or constant-voltage charg - ing modes, the prog pin voltage will be proportional to the actual charge current delivered to the batter y . there- fore, the actual charge current can be determined at any time by monitoring the prog pin voltage and using the following equation: i bat = v prog r prog ? 750 in many cases, the actual battery charge current, i bat , will be lower than i chg due to limited input current available and prioritization with the system load drawn from v out . thermal regulation to prevent thermal damage to the ic or surrounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110c. thermal regulation protects the ltc3554 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the ltc3554 or external components. the benefit of the ltc3554 thermal regula - tion loop is that charge current can be set according to the desired charge rate rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. charge status indication the chrg pin indicates the status of the battery charger. an open-drain output, the chrg pin can drive an indicator led through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charg - ing is complete, i.e., the charger enters constant-voltage mode and the charge current has dropped to one-tenth of the programmed value, the chrg pin is released (high impedance). the chrg pin does not respond to the c/10 threshold if the ltc3554 reduces the charge current due to excess load on the v out pin. this prevents false end of charge indications due to insufficient power available to the battery charger. even though charging is stopped during an ntc fault the chrg pin will stay low indicating that charging is not complete. op era t ion ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
17 battery charger stability considerations the ltc3554s battery charger contains both a constant- voltage and a constant-current control loop. the constant- voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, a 100f 1210 ceramic capacitor in series with a 0.3 resistor from bat to gnd is required to keep ripple voltage low if operation with the battery disconnected is allowed. high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. in constant-current mode, the prog pin is in the feed- back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the battery charger is stable with program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r prog 1 2 ? 100khz ? c prog ntc thermistor the battery temperature is measured by placing a nega - tive temperature coefficient (ntc) thermistor close to the batter y pack. t o use this feature connect the ntc therm - istor, r ntc , between the ntc pin and ground and a bias resistor, r nom , from v bus to ntc, as shown in figure 1. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r25). the ltc3554 will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r25 or approximately 54k (for a vishay curve 1 thermistor, this corresponds to approximately 40c). if the battery charger is in constant-voltage mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the temperature drops, the resistance of the ntc thermistor rises. the ltc3554 is also designed to pause charging when the value of the ntc thermistor increases to 3.17 times the value of r25. for a vishay curve 1 thermistor this resistance, 317k, corresponds to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscillation about the trip point. alternate ntc thermistors and biasing the ltc3554 provides temperature qualified charging if a grounded thermistor and a bias resistor are connected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25) the upper and lower temperatures are preprogrammed to approximately 40c and 0c, respectively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be adjusted by either a modification of the bias resistor value or by adding a second adjustment resistor to the cir cuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modified but not both. the other trip point will be determined by the characteristics of the thermistor . using the bias resistor in addition to an adjustment resistor, both the upper and the lower tem - perature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. examples of each technique are given below. op era t ion ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
18 ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n011-n1003f, used in the following examples, has a nominal value of 100k and follows the vishay curve 1 resistance-temperature characteristic. in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point r ntc|hot = value of the thermistor at the hot trip point r cold = ratio of r ntc|cold to r25 r hot = ratio of r ntc|hot to r25 r nom = primary thermistor bias resistor (see figure 2) r1 = optional temperature range adjustment resistor (see figure 2) the trip points for the ltc3554s temperature qualifica - tion are internally programmed at 0.35 ? v bus for the hot threshold and 0.76 ? v bus for the cold threshold. op era t ion figure 1. typical ntc thermistor circuit figure 2. ntc thermistor circuit with additional bias resistor ? + ? + r nom 100k r ntc 100k ntc v bus ntc_enable 3554 f01 ntc block too_cold too_hot 0.76 ? v bus (ntc rising) 0.35 ? v bus (ntc falling) 0.017 ? v bus (ntc falling) ? + 20 15 ? + ? + r nom 105k r ntc 100k r1 12.7k ntc v bus ntc_enable 3554 f02 too_cold too_hot 0.76 ? v bus (ntc rising) 0.35 ? v bus (ntc falling) 0.017 ? v bus (ntc falling) ? + 20 15 ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
19 opera t ion therefore, the hot trip point is set when: r ntc|hot r nom + r ntc|hot ? v bus = 0.35 ? v bus and the cold trip point is set when: r ntc|cold r nom + r ntc|cold ? v bus = 0.76 ? v bus solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.538 ? r nom and r ntc|cold = 3.17 ? r nom by setting r nom equal to r25, the above equations result in r hot = 0.538 and r cold = 3.17. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 40c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 40c. by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direction. the temperature span will change somewhat due to the nonlinear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r nom = r hot 0.538 ? r2 5 r nom = r cold 3.17 ? r25 where r hot and r cold are the resistance ratios at the de- sired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be independently set, the other is determined by the de- fault ratios designed in the ic. consider an example where a 60c hot trip point is desired. from the vishay curve 1 r-t characteristics, r hot is 0.2488 at 60c. using the above equation, r nom should be set to 46.4k. with this value of r nom , the cold trip point is about 16c. notice that the span is now 44c rather than the previous 40c. this is due to the decrease in temperature gain of the thermistor as absolute temperature increases. the upper and lower temperature trip points can be in- dependently programmed by using an additional bias resistor as shown in figure 2. the following formulas can be used to compute the values of r nom and r1: r nom = r cold ? r hot 2.714 ? r25 r1 = 0.536 ? r nom ? r hot ? r25 for example, to set the trip points to 0c and 45c with a vishay curve 1 thermistor choose: r nom = 3.266 ? 0.4368 2.714 ? 100k = 104.2k the nearest 1% value is 105k r1 = 0.536 ? 105k C 0.4368 ? 100k = 12.6k the nearest 1% value is 12.7k. the final solution is shown in figure 2 and results in an upper trip point of 45c and a lower trip point of 0c. ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
20 st e p-down switching regulator introduction the ltc3554 includes two constant-frequency current- mode 200ma step-down switching regulators, also known as buck regulators. at light loads, each regulator automatically enters burst mode operation to maintain high efficiency. applications with a near-zero-current sleep or memory keep-alive mode can command the ltc3554 switching regulators into a standby mode that maintains output regulation while drawing only 1.5a quiescent current per active regulator. load capability drops to 5ma per regulator in this mode. switching frequency and switch slew rate are pin-select - able, allowing the application circuit to dynamically trade off efficiency and emi per formance. the regulators are enabled, disabled and sequenced (ex - cept ltc3554-3) through the pushbutton interface (see the pushbutton interface section for more information). it is recommended that the step-down switching regulator input supply (bvin) be connected to the system supply pin (v out ). this is recommended because the undervoltage lockout circuit on the v out pin (v out uvlo) disables the step-down switching regulators when the v out voltage drops below the v out uvlo threshold. if driving the step- down switching regulator input supplies from a voltage other than v out , the regulators should not be operated outside their specified operating voltage range as opera - tion is not guaranteed beyond this range. output v oltage programming figure 3 shows the step-down switching regulator application circuit. the output voltage for each step-down switching regulator is programmed using a resistor divider from the step-down switching regulator output connected to the feedback pins (fb1 and fb2) such that: v outx = 0.8v ? r1 r2 + 1 ? ? ? ? ? ? typical values for r1 can be as high as 2.2m. (r1 + r2) can be as high as 3m. the capacitor c fb cancels the pole created by feedback resistors and the input capacitance of the fb pin and also helps to improve transient response for output voltages much greater than 0.8v. a variety of capacitor sizes can be used for c fb but a value of 10pf is recommended for most applications. experimentation with capacitor sizes between 2pf and 22pf may yield improved transient response. opera t ion figure 3. step-down switching regulator ap- plication circuit 3554 f03 0.8v v in c fb c out v outx mp mn gnd fbx r1 swx l pwm control en fsel r2 ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
21 pgood operation the pgood pin is an open-drain output which indicates that all enabled step-down switching regulators have reached their final regulation voltage. it goes high-impedance 230ms after all enabled switching regulators reach 92% of their regulation value. the delay allows ample time for an external processor to reset itself. pgood may be used as a power-on reset to a microprocessor powered by the step-down switching regulators. since pgood is an open-drain output, a pull-up resistor to an appropriate power source is needed. a suggested approach is to con - nect the pull-up resistor to one of the step-down switching regulator output voltages so that power is not dissipated while the regulators are disabled. in hard reset, the pgood pin is placed in high impedance state to minimize current draw from the batter y in this ul - tralow power state. this will cause the pgood pin to signal the wrong state (high level) if it is pulled up to a supply that is not shut down in hard reset (e.g. ba t). if pgood is pulled up to one of the step-down switching regulator outputs then the pgood pin will indicate the correct state (low level) in hard reset because the switching regulator output will be low. normal operating mode (stby pin low) in normal mode (stby pin low), the regulators perform as traditional constant-frequency current mode switching regulators. switching frequency is determined by an inter - nal oscillator whose frequency is selectable via the fsel pin. an internal latch is set at the start of ever y oscillator cycle, turning on the main p-channel mosfet switch. during each cycle, a current comparator compares the inductor current to the output of an error amplifier . the output of the current comparator resets the internal latch, which causes the main p-channel mosfet switch to turn off and the n-channel mosfet synchronous rectifier to turn on. the n-channel mosfet synchronous rectifier turns off at the end of the clock cycle, or when the current through the n-channel mosfet synchronous rectifier drops to zero, whichever happens first. via this mechanism, the error amplifier adjusts the peak inductor current to deliver the required output power. all necessary compensation is internal to the step-down switching regulator requiring only a single ceramic output capacitor for stability. at light load and no-load conditions, the buck automatically switches to a power-saving hysteretic control algorithm that operates the switches intermittently to minimize switching losses. known as burst mode operation, the buck cycles the power switches enough times to charge the output capacitor to a voltage slightly higher than the regulation point. the buck then goes into a reduced quiescent current sleep mode. in this state, power loss is minimized while the load current is supplied by the output capacitor. whenever the output voltage drops below a predetermined value, the buck wakes from sleep and cycles the switches again until the output capacitor voltage is once again slightly above the regulation point. sleep time thus depends on load current, since the load current determines the discharge rate of the output capacitor. standby mode (stby pin high) there are situations where even the low quiescent current of burst mode operation is not low enough. for instance, in a static memory keep alive situation, load current may fall well below 1a. in this case, the 25a typical bvin quiescent current per active regulator in burst mode opera - tion becomes the main factor determining battery run time. standby mode cuts bvin quiescent current down to just 1.5a per active regulator , greatly extending batter y run time in this essentially no-load region of operation. the application circuit commands the ltc3554 into and out of standby mode via the stby pin logic input. bringing the stby pin high places both regulators into standby mode, while bringing it low returns them to burst mode operation. in standby mode, load capability drops to 5ma per regulator. opera t ion ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
22 in standby mode, each regulator operates hysteretically. when the fb pin voltage falls below the internal 0.8v reference, a current source from bvin to sw turns on, delivering current through the inductor to the switching regulator output capacitor and load. when the fb pin voltage rises above the reference plus a small hysteresis voltage, that current is shut off. in this way, output regula - tion is maintained. since the power transfer from bvin to sw is through a high impedance current source rather than through a low impedance mosfet switch, power loss scales with load current as in a linear low dropout (ldo) regulator , rather than as in a switching regulator. for near-zero load condi - tions where regulator quiescent current is the dominant power loss, standby mode is ideal. but at any appreciable load current, burst mode operation yields the best overall conversion efficiency. shutdown each step-down switching regulator is shut down and enabled via the pushbutton inter face. in shutdown, each switching regulator draws only a few nanoamps of leak - age current from the bvin pin. each disabled regulator also pulls down on its output with a 10k resistor from its switch pin to ground. dropout operation it is possible for a step-down switching regulator s input voltage to fall near or below its programmed output volt- age (e.g., a battery voltage of 3.4v with a programmed output voltage of 3.3v). when this happens, the pmos switch duty cycle increases to 100%, keeping the switch on opera t ion continuously. known as dropout operation, the respective output voltage equals the regulators input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. soft-start operation in normal operating mode, soft-start works by gradually increasing the peak inductor current for each step-down switching regulator over a 500s period. this allows each output to rise slowly, helping minimize the inrush current needed to charge up the output capacitor. a soft-start cycle occurs whenever a given switching regulator is enabled. soft-start occurs only in normal operation, but not in standby mode. standby mode operation is already inher - ently current-limited, since the regulator works by inter - mittently turning on a current source from bvin to sw. changing the state of the stby pin while the regulators are operating doesnt trigger a new soft-start cycle, to avoid glitching the outputs. frequency/slew rate select the fsel pin allows an application to dynamically trade off between highest efficiency and reduced electromagnetic inter ference (emi) emission. when fsel is high, the switching regulator frequency is set to 2.25mhz to stay out of the am radio band. also, new patented cir cuitry is enabled which limits the slew rate of the switch nodes (sw1 and sw2). this new circuitry is designed to transition the switch node over a period of a few nanoseconds, significantly reducing radiated emi and conducted supply noise. ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
23 opera t ion when fsel is low, the frequency of the switching regulators is reduced to 1.125mhz. the slower switching frequency reduces switching losses and raises efficiency as shown in figures 4 and 5. switch node slew rate is also increased to minimize transition losses. as the programmed output voltage decreases, the difference in efficiency is more appreciable. low supply operation an undervoltage lockout circuit on the v out pin (v out uvlo) shuts down the step-down switching regulators when v out drops below about 2.6v. it is thus recom - mended that the step-down switching regulator input supply (bvin) be connected directly to the power path output (v out ). the uvlo prevents the step-down switching regulators from operating at low supply voltages where loss of regulation or other undesirable operation may occur . if driving the step-down switching regulator input supply from a voltage other than the v out pin, the regulators should not be operated outside the specified operating range as operation is not guaranteed beyond this range. inductor selection many different sizes and shapes of inductors are avail- able from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. figure 4. 1.2v output efficiency and power loss vs load current figure 5. 3.3v output efficiency and power loss vs load current load current (ma) 0.01 0.1 0 efficiency (%) power loss (mw) 70 100 1 10 100 1000 3554 f04 60 50 40 30 20 10 80 0 1000 10 1 0.1 100 90 bat = 3.8v fsel = l fsel = h efficiency power loss load current (ma) 0.01 0.1 0 efficiency (%) power loss (mw) 70 100 1 10 100 1000 3554 f05 60 50 40 30 20 10 80 0 1000 10 1 0.1 100 90 bat = 3.8v fsel = l fsel = h efficiency power loss ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
24 opera t ion inductor value should be chosen based on the desired output voltage. see table 2. table 3 shows several inductors that work well with the step-down switching regulators. these inductors offer a good compromise in current rat - ing, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. larger value inductors reduce ripple current, which im - proves output ripple voltage. lower value inductors result in higher ripple current and improved transient response time, but will reduce the available output current. t o maximize efficiency, choose an inductor with a low dc resistance. choose an inductor with a dc current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short circuit is a possible condition, the induc - tor should be rated to handle the maximum peak current specified for the step-down converters. different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar table 3. recommended inductors for step-down switching regulators inductor part no. l (h) max i dc (a) max dcr () size (l w h) (mm) manufacturer 1117as-4r7m 1117as-6r8m 1117as-100m 4.7 6.8 10 0.64 0.54 0.45 0.18* 0.250* 0.380* 3.0 2.8 1.0 toko www.toko.com cdrh2d11bnp-4r7n cdrh2d11bnp-6r8n cdrh2d11bnp-100n 4.7 6.8 10 0.7 0.6 0.48 0.248 0.284 0.428 3.0 3.0 1.2 sumida www.sumida.com sd3112-4r7-r sd3112-6r8-r sd3112-100-r 4.7 6.8 10 0.8 0.68 0.55 0.246* 0.291* 0.446* 3.1 3.1 1.2 cooper www.cooperet.com epl2014-472ml_ epl2014-682ml_ epl2014-103ml_ 4.7 6.8 10 0.88 0.8 0.6 0.254 0.316 0.416 2.0 1.8 1.4 coilcraft www.coilcraft.com * = t ypical dcr table 1. ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com table 2. choosing the inductor value desired output voltage recommended inductor value 1.8v or less 10h 1.8v to 2.5v 6.8h 2.5v to 3.3v 4.7h ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
25 electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best efficiency. the choice of which style inductor to use often depends more on the price versus size, performance and any radiated emi requirements than on what the step-down switching regulators requires to operate. the inductor value also has an effect on burst mode operation. lower inductor values will cause burst mode switching frequency to increase. input/output capacitor selection low esr (equivalent series resistance) ceramic capacitors should be used at both step-down switching regulator outputs as well as at the step-down switching regulator input supply. only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. for good transient response and stability the output capaci - tor for each step-down switching regulator should retain at least 4f of capacitance over operating temperature and bias voltage. generally, a good starting point is to use a 10f output capacitor. the switching regulator input supply should be bypassed with a 2.2f capacitor. consult with capacitor manufac - turers for detailed information on their selection and specifications of ceramic capacitors. many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. t able 1 shows a list of several ceramic capacitor manufacturers. pushbutton interface state diagram/operation figure 6 shows the ltc3554 pushbutton state diagram. figure 6. pushbutton state diagram 3554 f06 pup2 pdn1 pdn2 hrst hrst hrst por pwr_onx and uvlo pwr_onx extpwr or pb400ms 1sec 5sec 5sec 1sec pon poff pup1 hr pwr_onx or uvlo extpwr or pb400ms the pushbutton state machine has a clock with a 1.82ms period. upon first application of power, v bus or bat, an internal power on reset (por) signal places the pushbutton cir - cuitry into the power-down (pdn1) state. one second after entering the pdn1 state the pushbutton cir cuitr y will transition into the hard reset (hr) state. opera t ion ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
26 in the hr state, all supplies are disabled. the powerpath circuitry is placed in an ultralow quiescent state to minimize battery drain. if no external charging supply is present (v bus ) then the ideal diode is shut down, disconnecting v out from bat to further minimize battery drain. the ultra- low power consumption in the hr state makes it ideal for shipping or long term storage, minimizing battery drain. the following events cause the state machine to transition out of hr into the power-up (pup1) state: on input low for 400ms (pb400ms) application of external power (extpwr) upon entering the pup1 state, the pushbutton circuitry will sequence up the two step-down switching regula - tors, buck1 followed by buck2 (except ltc3554-3). in the ltc3554-3, buck1 and buck2 are simultaneously enabled. the p wr_on1 and pwr_on2 inputs are ignored in the pup1 state. the state machine remains in the pup1 state for five seconds. during the five seconds, the applications microprocessor, powered by the switching regulators, has time to boot and assert pwr_on1 and/or pwr_on2. five seconds after entering the pup1 state, the pushbut - ton circuitry automatically transitions into the power-on (pon) state. in the pon state, the switching regulators can be enabled and shut down at any time by the p wr_on1 and p wr_on2 pins. a high on pwr_on1 is needed to keep buck1 en - abled, and a high on pwr_on2 is needed to keep buck2 enabled. t o remain in the pon state, the application cir cuit must keep at least one of the pwr_on inputs high, else the state machine enters the power-down (pdn2) state. when pwr_on1 and pwr_on2 are both low, or when v out drops to its undervoltage lockout (v out uvlo) threshold, the state machine will leave the pon state and opera t ion enter the power-down (pdn2) state. in the power-down state (pdn2), both switching regulators are kept disabled regardless of the states of the pwr_on pins. the state machine remains in the power-down state for one second, before automatically entering the power-off (poff) state. this one second delay allows all ltc3554 generated sup - plies time to power down completely before they can be re-enabled. the same events used to exit the hard reset (hr) state are also used to exit the poff state and enter the pup2 state. the pup2 state operates in the same manner as the pup1 state previously described. both bucks remain powered up during the five second power-up (pup1 or pup2) period, regardless of the state of the pwr_on inputs. in either the hr or poff states, if any pwr_on pin is driven high, the pushbutton circuitry directly enters the pon state, without passing through the power-up (pup1 or pup2) states. this is because by asserting logic high on the pwr_on1 or pwr_on2 pins, the application has already told the ltc3554 exactly which buck(s) to turn on, so there is no need for an intermediate pup state in which both bucks are enabled for five seconds. starting from the hr state, bringing any pwr_on pin high enables the powerpath, if it wasnt already enabled due to v bus power being available. this powers up the v out pin from v bus or bat. when the v out voltage rises above the v out uvlo threshold, the state machine transitions from the hr state into the pon state, allowing the selected buck(s) to turn on. the hard reset (hrst) event is generated by pressing and holding the pushbutton ( on input low) for 5 seconds for ltc3554/ltc3554-1 (14 seconds for ltc3554-2 / ltc3554 - 3 ). for a valid hrst event to occur the button ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
27 bat 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 *buck1 and buck2 for the ltc3554-3 v bus on (pb) pbstat buck1* buck2 pgood pwr_on1 pwr_on2 state poff/hr pon pup2/pup1 3554 td01 5s 230ms 400ms figure 7. power-up via pushbutton press opera t ion press must start in the pup1, pup2 or pon state, but can end in any state. if a valid hrst event is present in pon, pdn2 or poff, then the state machine will transition to the pdn1 state and subsequently transition to the hr state one second later. debounced pushbutton output (pbstat) in the pon, pup1, and pup2 states, the pbstat open-drain output pin outputs a debounced version of the on push- button signal. on must be held low for at least 50ms for the pushbutton interface to recognize it and cause pbst at to go low. pbstat goes high impedance when on goes high, except the logic enforces a minimum pulse width on pbstat. once it goes low, it stays low for at least 50ms. in the hr, poff, pdn1, and pdn2 states, pbstat remains high impedance regardless of the state of on. power-up via pushbutton press figure 7 shows the ltc3554 powering up through ap - plication of the external pushbutton. for this example the pushbutton cir cuitr y starts in the poff or hr state with a battery connected and both bucks disabled. pushbutton application (on low) for 400ms transitions the pushbutton circuitry into the pup state and powers up buck1 followed by buck2 (except ltc3554-3). in the ltc3554-3, buck1 and buck2 power up at the same time. if either pwr_on is low or goes low after the 5 second period the corre - sponding buck(s) will be shut down. in the above example p wr_on2 is low at the end of the 5 second period and therefore buck2 is disabled at the end of the 5 second period. pgood is asserted once all enabled bucks are within 8% of their regulation voltage for 230ms. ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
28 the pwr_on inputs can be driven via a p/c or by one of the buck outputs through a high impedance (100k? typical) to keep the bucks enabled as described above. pbstat does not go low on initial pushbutton applica - tion for power-up, but will go low with subsequent on pushbutton applications in the pup1, pup2 or pon states. power-up via applying external power figure 8 shows the ltc3554 powering up through ap - plication of external power (v bus ). for this example the pushbutton circuitry starts in the poff or hr state with a battery connected and both bucks disabled. 100ms after v bus application the pushbutton circuitry transi - tions into the pup state and powers up buck1 followed by buck2 (except ltc3554-3). in the ltc3554-3, buck1 and buck2 power up at the same time. the 100ms delay time allows the applied supply to settle. the bucks will stay powered as long as their respective pwr_on inputs are driven high before the 5 second pup period is over. if either pwr_on is low or goes low after the 5 second opera t ion period the corresponding buck(s) will be shut down. in the above example both pwr_ons are high at the end of the 5 second period and therefore both bucks continue to stay on at the end of the 5 second period. pgood is asserted once all enabled bucks are within 8% of their regulation voltage for 230ms. the pwr_on inputs can be driven via a p/c or one of the buck outputs through a high impedance (100k? typ) to keep the bucks enabled as described above. without a battery present, initial power application causes a power-on reset which puts the pushbutton circuitry in the pdn1 state and subsequently the hr state one second later. at this time, if a valid supply voltage is detected at the bus pin (i.e., v bus > v uvlo and v bus C v bat > v duvlo ), the pushbutton circuity immediately enters the pup1 state. for this to work reliably, the bat pin voltage must be kept well-behaved when no battery is connected. ensure this by bypassing the bat pin to gnd with an rc network con - sisting of a 100f ceramic capacitor in series with 0.3. bat v bus on (pb) pbstat buck1 buck2* pgood pwr_on1 pwr_on2 state poff/hr *buck1 and buck2 for the ltc3554-3 pon pup2/pup1 3554 td02 5s 5s 230ms 100ms 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 8. power-up via applying external power ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
29 bat v bus on (pb) pbstat buck1 buck2 pgood pwr_on1 pwr_on2 state pon poff pdn2 3554 td04 1s c/p control 50ms c/p control 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 10. power-down via pwr_on de-assertion opera t ion power-up via asserting pwr_on pins figure 9 shows the ltc3554 powering up by driving pwr_on1 high. for this example the pushbutton circuitry starts in the poff or hr state with a battery connected and all bucks disabled. once pwr_on1 goes high, the pushbutton circuitry enters the pon state and buck1 powers up. once buck1s output is within 8% of its regu - lation voltage for 230ms, pgood is asserted. similarly, if p wr_on2 is brought high at a later time, buck2 will power up. the pushbutton cir cuitry remains in the pon state. during the time that buck2 powers up, pgood will be held low. pgood will be asserted again once buck2 is within 8% of its regulation for 230ms. powering up via pwr_on is useful for applications containing an always-on c thats not powered by the ltc3554 regulators. that c can power the application up and down for housekeeping and other activities not needing the users control. power-down via pwr_on de-assertion figure 10 shows the ltc3554 powering down by c/p control. for this example the pushbutton circuitry starts in the pon state with a battery connected and all bucks enabled. the user presses the pushbutton (on low) for at least 50ms, which generates a debounced, low impedance pulse on the pbstat output. after receiving the pbstat signal, the c/p software decides to drive the pwr_on inputs low in order to power down. after the last pwr_on pin goes low, the pushbutton circuitry will enter the pdn2 state. in the pdn2 state a one second wait time is initi - ated after which the pushbutton circuitry enters the poff state. during this one second time, the on and pwr_on inputs as well as external power application are ignored to allow all ltc3554 generated supplies to go low. though the above assumes a battery present, the same operation would take place with a valid external supply (v bus ) with or without a battery present. bat v bus on (pb) pbstat buck1 buck2 pgood pwr_on1 pwr_on2 state poff/hr pon 3554 td03 230ms 230ms 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 9. power-up via asserting pwr_on pins ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
30 holding on low through the one second power-down period will not cause a power-up event at end of the one second period. the on pin must be brought high following the power-down event and then go low again to establish a valid power-up event. uvlo minimum off-time timing (low battery) figure 11 assumes the battery is either missing or at a voltage below the v out uvlo threshold, and the applica- tion is running via external power (v bus ). a glitch on the external supply causes v out to drop below the v out uvlo threshold temporarily. this v out uvlo condition causes the pushbutton circuitry to transition from the pon state to the pdn2 state. upon entering the pdn2 state pgood will go low and the bucks power down together. in the typical case where the pwr_on1 and pwr_on2 pins are driven by logic powered by the bucks, the pwr_on1 and pwr_on2 pins would also go low, as depicted in figure 11. if the external supply recovers after entering the pdn2 state such that v out is no longer in uvlo, then the ltc3554 will transition back into the pup2 state once the pdn2 one second delay is complete. following the state diagram, the transition from pdn2 to pup2 in this case actually occurs via a brief visit to the poff state, during which the state machine immediately recognizes that valid external power is available and transitions into the pup2 state. entering the pup2 state will cause the bucks to power up as described previously in the power-up sections. not depicted here, but in the case where the pwr_on pins are driven by a supply other than the bucks, and are able to remain high while both bucks are off in the pdn2 state, then as per the state diagram in figure 6, once the one second pdn2 delay is over, the pushbutton circuitry enters the poff state. provided at least one pwr_on pin is high, and v out is no longer in uvlo, the pushbutton circuitry will transition directly into the pon state, enabling the buck(s) corresponding to the asserted pwr_on pin(s). note: if v out drops too low (below about 1.9v ) the ltc3554 will see this as a por condition and will enter the pdn1 rather than the pdn2 state. one second later the part will transition to the hr state. under these conditions an explicit power up event (such as a pushbutton press) may be required to bring the ltc3554 out of hard reset. hard reset timing hard reset provides an ultralow power-down state for shipping or long term storage as well as a way to power down the application in case of a software lockup. in the case of software lockup, the user can hold the pushbut - ton (on low) for 5 seconds for ltc3554/ltc3554-1 (14 seconds for ltc3554-2/ltc3554-3) and a hard reset event (hrst) will occur , placing the pushbutton cir cuitry in the power-down (pdn1) state. at this point the bucks will be shut down and pgood will go low. following a one second power-down period the pushbutton circuitry will enter the hard reset state (hr). opera t ion bat v bus on (pb) pbstat buck1 buck2 pgood pwr_on1 pwr_on2 state pon pon pup2 pdn2 3554 td05 5s 5s 1s, buck1 powers up buck2 powers up 230ms 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 figure 11. uvlo minimum off-time timing ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
31 holding on low through the one second power-down period will not cause a power-up event at end of the one second period. on must be brought high following the power-down event and then go low again for 400ms to establish a valid power-up event, as shown in figure 12. the regulators in figure 13 are slewing up with nominal output capacitors and no-load. adding a load or increasing output capacitance on any of the outputs will reduce the slew rate and lengthen the time it takes the regulator to get into regulation. in the ltc3554-3, buck1 and buck2 power up at the same time without sequencing. opera t ion bat v bus on (pb) pbstat buck1 buck2 pgood pwr_on1 pwr_on2 state pon pup1 hr pdn1 3554 td06 400ms 50ms t on_hr 1s 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 v out2 0.5v/div v out1 1v/div 0v 0v 3554 f13 100s/div figure 13. power-up sequencing figure 12. hard reset via holding on low layout and thermal considerations printed circuit board power dissipation in order to be able to deliver maximum charge current under all conditions, it is critical that the exposed pad on the backside of the ltc3554 package is soldered to a ground plane on the board. correctly soldered to a 2500mm 2 ground plane on a double-sided 1oz copper board, the ltc3554 has a thermal resistance ( ja ) of ap- proximately 70c/w. failure to make good thermal contact between the exposed pad on the backside of the package and an adequately sized ground plane will result in thermal resistances far greater than 70c/w . the conditions that cause the l tc3554 to reduce charge current due to the thermal protection feedback can be approximated by considering the power dissipated in the part. for high charge currents the ltc3554 power dis - sipation is approximately: p d = (v bus Cbat) ? i bat + p d(regs) where p d is the total power dissipated, v bus is the supply voltage, bat is the battery voltage, and i bat is the battery charge current. p d(regs) is the sum of power dissipated on chip by the step-down switching regulators. power-up sequencing (except ltc3554-3) figure 13 shows the actual power-up sequencing of the ltc3554. buck1 and buck2 are both initially disabled (0v). once the pushbutton has been applied (on low) for 400ms buck1 is enabled. buck1 slews up and enters regulation. the actual slew rate is controlled by the soft start function of buck1 in conjunction with output capacitance and load (see the step-down switching regulator operation sec - tion for more information). when buck1 is within about 8% of final regulation, buck2 is enabled and slews up into regulation. 230ms after buck2 is within 8% of final regulation, the pgood output will go high impedance. ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
32 opera t ion the power dissipated by a step-down switching regulator can be estimated as follows: p d(swx) = (b outx ? i out ) ? (100 - eff)/100 where b outx is the programmed output voltage, i out is the load current and eff is the % efficiency which can be measured or looked up on an efficiency table for the programmed output voltage. thus the power dissipated by all regulators is: p d(regs) = p d(sw1) + p d(sw2) it is not necessary to perform any worst-case power dis - sipation scenarios because the ltc3554 will automatically reduce the charge current to maintain the die temperature at approximately 110c. however , the approximate ambi - ent temperature at which the thermal feedback begins to protect the ic is: t a = 110c C p d ? ja example: consider the ltc3554 operating from a wall adapter with 5v (v bus ) providing 400ma (i bat ) to charge a li-ion battery at 3.3v (bat). also assume p d(regs) = 0.3w, so the total power dissipation is: p d = (5v C 3.3v) ? 400ma + 0.3w = 0.98w the ambient temperature above which the ltc3554 will be - gin to reduce the 400ma charge current, is approximately: t a = 110c C 0.98w ? 70c/w = 41.4c the ltc3554 can be used above 41.4c, but the charge current will be reduced below 400ma. the charge current at a given ambient temperature can be approximated by: p d = (110c C t a ) / ja = (v bus C bat) ? i bat + p d(regs) thus: i bat = [(110c C t a ) / ja - p d(regs) ] (v bus C bat) consider the above example with an ambient tem - perature of 60c. the charge current will be reduced to approximately: i bat = [(110c - 60c) / 70c/w - 0.3w]/(5v C 3.3v) i bat = (0.71w - 0.3w) / 1.7v = 241ma printed circuit board layout when laying out the printed circuit board, the following list should be followed to ensure proper operation of the ltc3554: 1. the exposed pad of the package (pin 21) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2. the trace to the step-down switching regulator input supply pin (bvin) and its decoupling capacitor should be k ept as short as possible. the gnd side of this capacitor should connect directly to the ground plane of the part. this capacitor provides the ac current to the internal power mosfets and their drivers. it is important to minimize inductance from this capacitor to the pin of the ltc3554. connect bvin to v out through a short low impedance trace. 3. the switching power traces connecting sw1 and sw2 to their respective inductors should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the switching nodes, sensitive nodes such as the feedback nodes (fb1 and fb2) should be kept far away or shielded from the switching nodes or poor per formance could result. 4. connections between the step-down switching regu - lator inductors and their respective output capacitors should be kept as short as possible. the gnd side of the output capacitors should connect directly to the thermal ground plane of the part. 5. keep the buck feedback pin traces (fb1 and fb2) as short as possible. minimize any parasitic capacitance between the feedback traces and any switching node (i.e., sw1, sw2 and logic signals). if necessary , shield the feedback nodes with a gnd trace. 6. connections between the ltc3554 powerpath pins (v bus and v out ) and their respective decoupling ca - pacitors should be kept as short as possible. the gnd side of these capacitors should connect directly to the ground plane of the part. ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
33 typical a pplica t ion v bus ntc prog hpwr susp pwr_on1 fsel stby pgood pwr_on2 pbstat on v out chrg bat bvin sw1 fb1 sw2 fb2 gnd 3 cell alkaline or lithium c1 10f 20 u1 u2 16 1 19 9 2 10 4 8 3 5 pb1 7 11 6 13 12 17 18 14 15 r prog 1.87k c3 10pf c4 10f c2 2.2f r up1 1m r up2 590k r lo1 464k 2.5v l1 10h c5 10pf r4 100k r2 100k r3 100k c6 10f r lo2 464k 1.8v l2 10h system load 4.35v to 5.5v usb input ltc3554 i/o core pbstat pgood stby fsel en susp hpwr 3554 f14 c + figure 14. 3-cell alkaline/lithium with powerpath (charger disabled) ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
34 p ackage descrip t ion 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.20 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 19 20 2 0.40 bsc 0.200 ref 2.10 0.05 3.50 0.05 (4 sides) 0.70 0.05 0.00 ? 0.05 (ud20) qfn 0306 rev a 0.20 0.05 0.40 bsc package outline ud package 20-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1720 rev a) ud package 20-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1720 rev a) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
35 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 7/10 pd package information removed and ud package information added to data sheet update to typical application ltc3554eud added and ltc3554epd designated obsolete in order information section note 2 updated pin 21 description updated updated related parts 1 to 16 1 2 5 12 36 b 01/11 ltc3554-2 option added. reflected throughout the data sheet 1 to 36 c 10/11 ltc3554-1 option added. reflected throughout the data sheet 1 to 36 d 01/12 corrected title on axis of graph g23 updated block diagram added text to state diagram/operation section 10 13 25 e 08/12 added new part number ltc3554-3 added options table throughout 2 f 04/15 changed ja of package from 70c/w to 58.7c/w 2 ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff
36 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0415 rev f ? printed in usa r ela t e d p ar t s part number description comments ltc3455 dual dc/dc converter with usb power manager and li-ion battery charger seamless transition between input power sources: li-ion battery, usb and 5v wall adapter, 4mm 4mm qfn-24 package ltc3456 2-cell, multioutput dc/dc converter with usb power manager seamless transition between 2-cell battery, usb and ac wall adapter input power sources, 4mm 4mm qfn-24 package ltc3557 usb power manager with li-ion charger, triple step-down dc/dc regulators triple step-down switching regulators (600ma, 400ma); 4mm 4mm qfn package ltc3559 usb charger with dual buck regulators adjustable, synchronous buck converters, 3mm 3mm qfn-16 package ltc4080 500ma standalone charger with 300ma synchronous buck charges single-cell li-ion batteries, timer termination + c/10, thermal regulation, buck output: 0.8v to v bat , buck input v in : 2.7v to 5.5v, 3mm 3mm dfn-10 package ltc3553 power pmic/charger/buck/ldo 3mm 3mm 0.75mm qfn-20 package typical a pplica t ion v bus ntc prog hpwr susp pwr_on1 fsel stby pgood pwr_on2 pbstat on v out chrg bat bvin sw1 fb1 sw2 fb2 gnd li-ion battery c1 10f r3 r1 100k 20 16 1 19 9 2 10 4 8 3 5 pb1 7 11 6 13 12 17 18 14 15 r prog 1.87k t c3 10pf c4 10f c2 2.2f r up1 r up2 2.05m r lo1 649k 3.3v ldo 1.8v l1 4.7h c5 10pf c6 10f 332k r lo2 649k 1.2v l2 10h system load 4.35v to 5.5v usb input ltc3554 i/o core pbstat pwr_on2 pgood stby fsel pwr_on1 susp hpwr 3554 f15 c memory en r2 100k r2 100k r3 100k + c7 10f figure 15. usb powerpath with li-ion battery (ntc qualified charging) ltc3554/ltc3554-1/ ltc3554-2/ltc3554-3 3554123ff

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